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UK funding (£1,938,930): The world’s first on-chip and in-life monitoring solution to rapidly detect cyber security threats in Connected and Autonomous Vehicles (CAVs) Ukri1 Dec 2019 UK Research and Innovation, United Kingdom
Overview
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The world’s first on-chip and in-life monitoring solution to rapidly detect cyber security threats in Connected and Autonomous Vehicles (CAVs)
| Abstract | Connected and Autonomous Vehicles (CAVs), as part of the Internet of Things (IoT), represent a major cyber security challenge. In 2015, Charlie Miller, a security researcher at Twitter, and Chris Valasek, director of Vehicle Security Research at IOActive, exposed the security vulnerabilities in automobiles by hacking into a Fiat-Chrysler Jeep Cherokee remotely, controlling the cars' various controls from the radio volume to the brakes and steering wheel. Since then, nearly all OEMs have suffered similar cyber-attacks. The socio-economic impacts of cyber security attacks are tremendous, with the automotive industry estimated to lose £26 billion annually by 2023 [Upstream Security]. Systems-on-chip (SoCs) integrate all computing components that power today's CAVs operating within a digitally connected societal framework via the Internet of Things (IoT). A clear market need exists to monitor SoCs 'in-life' (i.e. in an operating environment rather than in the lab), and this is further mandated by current international standards (ISO 26262 "Road Vehicles - Functional Safety") and forthcoming standards (ISO 21434 "Road Vehicles - Cybersecurity engineering"). However, existing software monitoring solutions: Take hundreds of milliseconds to detect anomalies, which is inadequate for safety-critical applications. At ~70 mph, a CAV will travel 22 meters in 700 milliseconds, which could be critical to avoid an accident. Disturb the normal operation of the SoC. Are highly visible and more prone to hacking. Are unable to monitor the entire SoC. Today, no hardware-based, in-life SoC monitoring solution exists. UltraSoC provides on-chip monitoring solutions to monitor the health of SoCs during the design phase and our customers include major firms such as Intel, HiSilicon (Huawei), C-SKY (Alibaba) and more. However, unlike our competitors, our IP is runtime configurable, vendor-neutral, and being hardware-based allows us to detect anomalies at 'clock-speed' (i.e. in microseconds), which is 1,000x faster than software. Being embedded into the SoC itself during the design phase gives us a unique opportunity to exploit our existing IP to monitor SoC health in-life. However, reliably monitoring SoCs in-life poses significant technical challenges, especially to discriminate normal and abnormal system behaviour in constantly changing operating environments. This project will develop the world's first on-chip and in-life monitoring solution to detect system anomalies at clock-speed, be vendor-neutral, non-intrusive, runtime configurable and far less prone to hacking. This will ensure IoT systems function as they were designed, protecting citizens and infrastructure. |
| Category | Collaborative R&D |
| Reference | 105591 |
| Status | Closed |
| Funded period start | 01/12/2019 |
| Funded period end | 28/02/2022 |
| Funded value | £1,938,930.00 |
| Source | https://gtr.ukri.org/projects?ref=105591 |
Participating Organisations
| MENTOR GRAPHICS (UK) LIMITED |
£838,285.00 |
| COPPER HORSE LIMITED |
£642,574.00 |
| COVENTRY UNIVERSITY |
£298,076.00 |
| UNIVERSITY OF SOUTHAMPTON |
£159,995.00 |
The filing refers to a past date, and does not necessarily reflect the current state. The current state is available on the following page: Siemens Electronic Design Automation Ltd., Farnborough.
